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      "content": "You need to set [`SYNTH_EXCLUDED_CELL_FILE`](https://librelane.readthedocs.io/en/latest/reference/common_pdk_vars.html) to point to your exclude file.",
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      "content": "You can find the current one in `gf180mcu/gf180mcuD/libs.tech/librelane/gf180mcu_fd_sc_mcu7t5v0/synth_exclude.cells`",
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      "content": "it is possible to overlay it?",
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      "content": "I don't want to touch the gf180mcu repo",
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      "content": "No, unfortunately not. Make a copy of the file in your repository and add the line.",
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      "content": "Yes, that's what I did",
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      "content": "But it'd be really nice to understand the actual issue",
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      "content": "But if they are changes in gf180mcu you will not recognize \ud83d\ude42",
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      "content": "Today you know, but not tomorrow \ud83d\ude42",
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      "content": "Yes, the proper solution is to fix the simulation model of the cell (if that is the issue).",
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      "content": "$ cat 06-yosys-synthesis/chip_top.nl.v  | grep gf180mcu_fd_sc_mcu7t5v0__oai21_1 | wc -l\n0\nlolo",
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      "content": "There's a good chance the simulation model is not the issue, since there are many `gf180mcu_fd_sc_mcu7t5v0__oai21_2` instances in the design that does pass the GL tests",
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      "content": "what is the issue then?",
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